Skip to main content

Powerlattice Technologies Inc.

Senior or Staff Embedded Software Engineer

Chandler, Arizona, United States

Location
Chandler, Arizona, United States
Work
On-site
Employment
Full-time
Level
Lead / staff
Function
Engineering
Pay
$130K – $190K a year (read from the ad)
Posted
3 weeks ago

Pay and the market here

The top of this role’s range, $190K a year, is 5% below the median of $200K for lead / staff engineering jobs in Arizona (middle half $174K – $250K, 25 jobs that state pay).

47 engineering jobs open in Chandler: 2% remote, 4 posted in the last 30 days.

Wondering how well you fit this one? OptiTalent Career checks each requirement against your own record, privately. About OptiTalent Career →

About the role

Senior/Staff Embedded Software Engineer

Reports to SVP Systems and Applications

About Us

Powerlattice is a well-funded semiconductor start-up company backed by well-known large Silicon Valley VCs. The company is working on the industry’s groundbreaking chiplet solution for a fundamental shift in how high-performance chips get powered, paving the way for the next generation of AI and advanced computing.

About the Role

We are seeking a Senior/Staff Embedded Software Engineer who is excited to work at the intersection of firmware, automation, and silicon validation for next-generation Power Delivery Chiplets. In this role, you will build both embedded firmware (C on microcontrollers) and scalable Python-based validation infrastructure that directly impacts product quality and time-to-market.

You will have the opportunity to own critical pieces of the validation stack—from low-level firmware controlling hardware platforms to high-level automation frameworks, data systems, and customer-facing debug tools. The role offers broad exposure to silicon bring-up, lab automation, and system-level debugging, making it ideal for engineers who want to deepen their expertise across both embedded systems and software infrastructure.

As part of a highly collaborative environment, you’ll work closely with hardware, firmware, and silicon design teams, gaining hands-on experience with real-world power management systems and complex hardware interfaces. This role provides strong opportunities to grow into technical leadership, drive architecture decisions, and shape the validation ecosystem for future products.

Key Responsibilities

  • Design and implement Python-based validation frameworks, drivers, and automation tools
  • Build and maintain scalable validation infrastructure, including regression systems
  • Design device drivers, board-support packages, hardware interfaces, and low-level firmware
  • Develop GUIs and tools for customer debug and evaluation kits
  • Create and maintain databases for test logs, results, and analysis
  • Debug system-level issues across firmware, software, and hardware interfaces
  • Collaborate with hardware, validation, and silicon teams during bring-up and testing
  • Develop embedded firmware in C for microcontrollers

Qualifications

This role is onsite based in Chandler, AZ

  • B.S or M.S. in electrical engineering or related fields
  • 7+ years of bring-up/embedded firmware level SW development experience
  • Strong Python skills for automation, scripting, and test framework development
  • Experience with embedded system bring-up and debugging
  • Familiarity with communication interfaces: I2C, SPI, I3C, JTAG
  • Experience automating and controlling lab instruments (DMMs, Oscilloscopes, Power supplies, etc.)
  • Solid understanding of embedded systems fundamentals (interrupts, peripherals, timing, etc.)
  • Experience with databases for validation data management
  • Experience developing GUI applications

Preferred Qualifications

  • Experience in one or more areas such as wireless, networking, motor control, power management, sensors, security, bootloaders, or high-performance compute
  • Silicon bring-up experience
  • Firmware programming and debug
  • Manufacturing deployment and debug experience
  • Ability to read schematics and support board-level debug (analog/digital)

Compensation & Benefits

Anticipated annual base salary: $130,000 - $190,000

  • Competitive salary, stock option grant and benefits package
  • Health, dental, vision, 401(k), etc.

Source

Posted by Powerlattice Technologies Inc. on their own hiring page, jobs.ashbyhq.com. OptiTalent shows it as published, read 07 Nov 2026 12:00 UTC; the original is the reference.

View the original ad ↗

More at Powerlattice Technologies Inc.

  • Powerlattice Technologies Inc. · Vancouver, Washington, United States +1

    HybridFull-timeLead / staff$160K – $190K a yearEngineering

    We are seeking an experienced and hands-on Design Verification Lead to spearhead verification activities for complex SoC/IP designs, developing scalable SystemVerilog-based verification environments, verification strategies, reusable test infrastructure, and automated…

  • Powerlattice Technologies Inc. · Chandler, Arizona, United States

    On-siteFull-time$165K – $240K a yearEngineering

    We are seeking a highly skilled and hands-on Applications Engineer to support key customer accounts. The engineer will lead laboratory evaluation of chiplet power converters for AI and advanced computing. This involves test setup and debugging for focused customer accounts to…

  • Powerlattice Technologies Inc. · Vancouver, Washington, United States

    HybridFull-time$130K – $150K a yearOperations

    Powerlattice is a well-funded semiconductor start-up company backed by well-known large Silicon Valley VCs. The company is working on the industry’s groundbreaking chiplet solution for a fundamental shift in how high-performance chips get powered, paving the way for the next…

  • Powerlattice Technologies Inc. · Chandler, Arizona, United States

    HybridFull-timeSenior$150K – $200K a yearEngineering

    We are seeking an experienced and hands-on Senior Digital Design Engineer to contribute to the design and implementation of complex digital systems and SoC components. This role offers the opportunity to own significant functional blocks from microarchitecture through RTL…