Skip to main content

Volantis Semiconductor, Inc.

Link Validation Engineer

San Francisco, California, United States +2

Location
San Francisco, California, United States · Austin, Texas, United States · Boston, Massachusetts, United States
Work
Hybrid
Employment
Not stated
Level
Not stated
Function
Engineering
Pay
Not stated
Posted
3 months ago

Pay and the market here

5,003 engineering jobs open in San Francisco: 9% remote, 949 posted in the last 30 days.

Wondering how well you fit this one? OptiTalent Career checks each requirement against your own record, privately. About OptiTalent Career →

About the role

What We’re Looking For

We’re looking for link validation engineers to help with DVT and bringup of the core optical link and PHY.

Ideal Background

Ideal candidates for this role should have:

  • Hands-on experience with the bringup and DVT process of optical links and PHYs
  • Deep understanding of both PHY systems (both electrical and optical) and optical links (TDECQ, jitter, BER, etc)
  • Hands-on experience with contributing to the design process of PHYs and ideally electro-optic PHYs

Nice to Have

  • Experience with clock forwarded optical links
  • Experience with both copper SERDES system bringup as well as optical PHY system bringup
  • Experience with wide and slow optical architectures

Source

Posted by Volantis Semiconductor, Inc. on their own hiring page, job-boards.greenhouse.io. OptiTalent shows it as published, read 07 Nov 2026 11:26 UTC; the original is the reference.

View the original ad ↗

More at Volantis Semiconductor, Inc.

  • Volantis Semiconductor, Inc. · San Francisco, California, United States +2

    HybridOperations

    We're looking for technical program managers to own programs across our wafer-scale photonic systems. Each TPM owns one program and works embedded with the engineering team that carries most of it, from packaging and assembly to silicon and system bring-up. We have two openings.

  • Volantis Semiconductor, Inc. · San Francisco, California, United States

    HybridEngineering

    Partnering with the laser design team to define test plans, specifications and pass/fail criteria for new individually addressable VCSEL array designs.; Characterizing prototype devices (LIV, spectral, far-field/beam profile, polarization, thermal and high-speed modulation) and…

  • DFT Lead

    3 months ago

    Volantis Semiconductor, Inc. · San Francisco, California, United States +2

    HybridLead / staff

    We’re looking for DFT engineers to contribute to and own DFT efforts for blocks and entire dies on the A-0 and A-1 wafer-scale systems.

  • SoC Architect

    3 months ago

    Volantis Semiconductor, Inc. · San Francisco, California, United States +2

    HybridLead / staff

    We’re looking for SoC architects to own the detailed SoC-level architecture of dies on the A-0 and A-1 wafer-scale systems. You will work with the architecture and ASIC design teams to create implementable specs and drive the execution of said implementations.