AI Silicon, Design Verification

About Unconventional

Since 2022, AI has entered the mainstream, reshaping entire industries from education and software development to fundamental consumer behaviors. This revolution has created an unprecedented demand for computation - a demand that is now fundamentally limited by energy, not just in the datacenter, but at a global scale.

At Unconventional, our mission is to solve this. We are rethinking computing from the ground up to build a new foundation for AI that is 1000x more efficient. We're doing this by exploiting the rich physics of semiconductors, mapping neural networks directly to the device physics rather than relying on layers of inefficient abstraction.

Responsibilities

• Verification Strategy & Architecture: Define, architect, and implement comprehensive verification plans and environments for IP blocks and full chip from specification to tape-out.
• Methodology and Infrastructure: help build verification infrastructure from ground zero to flexible and nimble environments, able to move quickly and scale for growth.
• Testbench Ownership: Take full ownership of the verification lifecycle, including the development and maintenance of scalable testbenches, sophisticated test cases, and robust verification environments.
• Advanced Methodology Execution: Deploy industry-standard methodologies (UVM/SystemVerilog) to conduct constrained-random stimulus generation, coverage-driven verification, and assertions.
• Cross-Functional Integration: Collaborate closely with digital and analog design teams, as well as software and systems teams, to define verification requirements, debug complex hardware/software interactions, and ensure design integrity.
• Analysis & Closure: Perform exhaustive analysis of functional and code coverage. Debug failures at the RTL and gate level to ensure 100% verification closure and high-quality silicon.

Minimum Qualifications

• Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• Experience: Minimum of 8 years of hands-on experience with advanced verification methodologies and languages, specifically UVM and SystemVerilog.
• Technical Expertise: Proven track record of developing and maintaining complex verification testbenches and automated test environments.
• Scripting Experience: Proficiency in scripting languages (e.g., Python, Shell, or Bash) for automation of verification flows and result analysis
• Tool and Infrastructure Knowledge: Strong familiarity with general-purpose operating systems such as Linux, and industry standard tools from companies such as Cadence and Synopsys.

Preferred Qualifications (Nice to Have)

• Master's degree or Ph.D. in Electrical Engineering or Computer Science, with a specific emphasis on computer architecture.
• Expert-level knowledge of UVM architecture and high-level behavioral modeling.
• Experience with modern AI-driven code generation tools

Why Join Us?

• The Mission: Redefine computing for the next 50 years by solving the fundamental energy limitation of AI at a global scale.
• The Impact: Shape the company's future as a foundational team member. Enjoy massive ownership and an outsized opportunity to drive change.
• The Challenge: Dive into deeply complex, intellectually stimulating, and unsolved problems at the cutting edge of multiple, converging fields.
• The Perks: A comprehensive package including best-in-class health benefits, 401k matching, truly unlimited PTO, and complimentary meals in our Palo Alto office.